The process of identifying and correcting problems in new integrated circuit (IC) designs is known as debugging. During debugging, it is sometimes necessary to edit (i.e., add, delete or reroute) signal line connections within the IC in order to optimize its performance. After debugging, optimized designs can be used to mass produce integrated circuits.
FIG. 1 shows a schematic illustration of how an IC 100 can be edited. Here, circuit block 102 is coupled to circuit block 104 by way of inverter 106. If during debugging it is determined that the signal from circuit block 102 should not be inverted when received by circuit block 106, then IC 100 can be edited by (1) cutting the signal line at point 114 to electrically remove inverter 106 from IC 100, and (2) coupling circuit block 102 to circuit block 104 at points 108 and 110 by way of jumper 112.
Prior art techniques for cutting signal lines to isolate circuitry include removing portions of a first level metal (M1) interconnect using a focused ion beam (FIB) milling tool. These techniques are discussed in U.S. Pat. No. 6,153,891, entitled “Method and Apparatus Providing A Circuit Edit Structure Through The Back Side of An Integrated Circuit,” filed on Sep. 30, 1997, and assigned to the Assignee hereof. FIG. 2 illustrates a cross-sectional view 200 showing one way this can be done.
Shown in FIG. 2 is a cross-sectional view of a portion of an IC 200 that includes source/drain region 225 of transistor 226 and source/drain region 227 of transistor 228 (e.g., the output of the inverter 106 and input of circuit block 104 in FIG. 1) formed in semiconductor substrate 222 and separated by isolation region 224. First level (M1) interconnect 231 couples source/drain 225 to source/drain 227 by way of vias 229 formed in dielectric 230. Second level (M2) interconnects 233 can connect to M1 interconnect 231 through vias in some regions (not shown). In other regions, the M1 interconnect 231 is isolated from M2 interconnects 233 by way of interlayer dielectric 232. Layer 234, which can include any number of other conductors, insulators, etc., can overlie interlayer dielectric 232.
As shown in FIG. 2, the signal line 231 can be cut by milling a window opening 235 through the silicon substrate 222. After the window 235 is milled, portions of the isolation region 224, portions of the dielectric 230, and then portions of the first level interconnect 231 exposed by the window 135 are removed until a discontinuity 214 is created in M1 interconnect 231. The discontinuity 214 creates an electrical open (similar to the cut 114 schematically shown in FIG. 1) that electrically isolates source/drain region 225 from source/drain region 226.
The migration from aluminum to copper interconnects in state-of-the-art semiconductor processes has made the cutting process described in FIG. 2 problematic. More specifically, because copper does not easily volatilize, it is difficult to cut using FIB enhanced/assisted chemical etch tools, lasers, etc. This can result in failure to isolate existing circuitry (due to incomplete cuts) and copper redeposition that can produce shorts between adjacent interconnects (not shown). The FIB's energy can be increased to address this, however this reduces selectivity to the adjacent interlayer dielectric 232 and creates other problems. For example, now the loss in selectively in conjunction with the copper's low volatility can result in electrical shorts 236 between M1 interconnects 231 and M2 interconnect 233, as shown in FIG. 2.
It will be appreciated that for simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.